1. Field of The Invention
The present invention relates to an electronic circuit apparatus for providing a stable clock into a semiconductor integrated circuit apparatus such as LSI, IC, etc. or between the apparatuses.
2. Prior Art
Recently, among the electronic circuit apparatuses, more specifically, LSIs, a speeding-up of processing is advanced. Presently, LSI operating at 500 Mhz or more is already published (K. Suzuki et al. ISSCC94, pp.214 to pp.215). It is an important key for the speeding-up to minimize a phase shift in such an LSI and between LSIs, that is, to minimize a clock skew. The clock skew in question will be explained by using FIGS. 1A and 1B. A clock signal is outputted from a clock buffer 60 via an output terminal 61. The clock signal is supplied to a first logic circuit 64 and a second logic circuit 65, and the first logic circuit 64 and the second logic circuit 65 are operated. Supposing that the first logic circuit 64 is located near the clock buffer 60, on one hand, a wire 62 to the second logic circuit 65 is as long as, for example, a distance from one end to the other end of a chip. In this case, compared to a signal 61a received by the first logic circuit 64, a signal 63a received by the second logic circuit 65 is delayed by a wire delay. This signal phase shift .DELTA.t is called a clock skew.
As one of methods of reducing the clock skew, heretofore, there is such a method that the wire delay from a clock source to a receiver which each clock is provided to is compensated by a delay circuit generating about as much delay as this wire delay. However, the wire delay is different from the delay of a delay compensation circuit due to a dispersion occurred in a process such as a process of preparing a semiconductor, etc.
That is, for example in the process of preparing a semiconductor apparatus, since there are occurred a resistance dispersion due to the dispersions of the wire width and a film thickness and a wire parasitic capacity dispersion due to the dispersion of insulating films at an upper and a lower of the wire, the wire delay determined by a resistance R and a capacity C is dispersed. While, for example, if the delay circuit comprises series CMOS inverters, this delay is dispersed by a threshold value dispersion due to the dispersions of a gate length of a MOS transistor, an impurity profile, a gate oxide film thickness, etc., a current drive ability dispersion and the like. Since a cause of the delay dispersion of the wire is different from that of the delay dispersion of the delay compensation circuit, both of the delays are not interlocking-varied. Accordingly, even if a delay time is set according to a certain semiconductor apparatus, this delay time is different from the delay time of another prepared semiconductor apparatus. Thereby, since the clock skew is generated, sometimes, a circuit cannot be normally operated.
In such a manner, in conventional semiconductor apparatuses such as LSI, IC, etc., there has been no semiconductor apparatus which is strong relative to a process dispersion, etc., and can stably provide the clock, and can ensure a normal operation of the circuit.